Phase-locked loops (PLLs) are an integral part of many electronics circuits and are particularly important in communication circuits. For example, many digital systems use clock signals to trigger synchronous circuits (e.g., flip-flops). Clock signals are common in wireless devices (such as but not limited to cellular phones for example) via their digital circuitry, where the transmitter and receiver systems use local oscillator (LO) signals for frequency conversions. Typically, it is the clock and LO signals that are often generated with PLLs.
Further, PLLs have a broad range of uses and applications ranging from microprocessors to memory devices (DRAM and DDR) and to clock and data recovery in a communication system, for example.
As used herein, it is understood that the term microprocessor is intended to mean but not be exclusively limited to a processor for performing processing typically implemented as a microchip, a logic chip, in a logic method, and similar. The microprocessor is intended and designed to perform arithmetic and logic operations that make use of small number-holding areas called registers, operatively executed by a set of instructions that are part of the microprocessor's design. While a microprocessor relies on instructions for execution, it is not limited to using instructions from the basic input/output system (BIOS) that may come with a related computer as part of its memory or an application program.
As used herein, it is further understood that DRAM is intended mean Dynamic Random Access Memory (DRAM) and DDR is intended to mean DDR SDRAM (Double Data Rate SDRAM). At present, DRAM is the most common kind of random access memory (RAM) for personal computers (PCs) and workstations, where the random access aspects are intended to mean that the PC processor can access any part of the memory or data storage space directly rather than having to proceed sequentially from some starting place. DRAM is dynamic in that, unlike static RAM (which may also be referred to as Static Random Access Memory or SRAM), it needs to have its storage cells refreshed or given a new electronic charge every few milliseconds. Contradistinctively, DDR SDRAM is synchronous dynamic RAM (SDRAM) that improves memory clock speed as it activates output on both the rising and falling edge of the system clock rather than exclusively on the rising edge.
Recently, a PLL for clock signal generation has been an essential design building block in integrated circuit systems. The quality of clock signal generation, also used herein as “clock” or “clocks” (i.e., a clock signal is a signal used to relate the activities of two or more circuits, such as synchronization, in which the signal typically oscillates between a high and a low state, with a given duty cycle.), generated by a PLL plays an important role in determining the performance of a circuit and its system. Especially, in today's applications, the technology trend of higher frequency and faster data processing rate results in using both rising and falling edges of the clock. Furthermore, in recent times, it is becoming more common for a system to operate with multiple phases of a clock simultaneously.
As a result, to better the possibility of effective operation, operative restraints placing a strict imposition on the duty cycle of such clocks should be encouraged. For instance, in a given system, duty clocks operating at 50% duty cycle do support a broader timing margin and hence will likely results in improved system performance, improved tolerance to temperature and semiconductor process variations, and the like.
FIG. 1 depicts a conventional PLL architecture used in a typical system with a memory interface, collectively 100.
In FIG. 1, a system PLL 105 generates system clocks at 110 for an internal memory controller 115. The internal memory controller 115 has a built-in digital delay-locked loop (DLL) circuit for clock phase adjustment. The system clock 110, at the same time, is also the input reference clock to the de-skew PLL 120, following pass through at the buffer 125 which has an adjustable time delay. Typically, in the conventional PLL, the de-skew PLL typically “zeroes out” the input-output (I/O) path delay such that external memories, double-data rate (DDR) memory and/or synchronous random access memory (SDRAM), 129, are triggered simultaneously as it is at the memory controller 115. More specifically, CKIN and CKDDR, 130 and 135 respectively in FIG. 1, are precisely aligned in time. The buffer 125 may typically be used to extend the deskew time range.
As becomes apparent from FIG. 1, there are two critical limitations, in addition to a series of significant deficiencies, in this conventional PLL architecture, especially when viewed with particularity to high-speed applications.
Firstly, the duty cycle of the clock from de-skew PLL 120 needs to be maintained to as close to 50% as is possible so as to better the timing margin and tolerance for a DDR memory environment, 129. This is required since both rising and falling edges of the clock are being employed to trigger DDR 129. Secondly, total loop delay time that CKOUT experiences, including clock buffers, package, board trace, capacitive loading, and I/O transmitter (TX) 140 and receiver (RX) 145, may exceed a clock period in high-speed operation. Therefore, since pole location of the de-skew PLL is nonlinearly affected by the total loop delay time, as loop delay time is increased, the phase margin of de-skew PLL is consequently reduced.
Unfortunately, conventional PLLs usually include a voltage-to-current (V-I) converter between the loop filter (LF) and the voltage-controlled oscillator (VCO). In a conventional PLL, the V-I converter serves the purpose of converting the LF voltage to VCO biasing current, such that the VCO oscillation frequency is adjusted by the loop filter voltage. An unintended result is that the V-I converter could introduce linearity and dynamic range issues to the overall PLL response. Additionally, the V-I converter will likely require additional power consumption and die area.
Similarly, when applying a conventional PLL for deskewing purposes, the conventional PLL in unable to tolerate long loop delay times, such as those that may be for a clock period or more, for example. One known step to this overcome this issue is to include a large loop capacitor with the conventional PLL in order to stabilize the closed-loop response. However, even with this added step, the resulting loop delay time of the conventional PLL with the large loop capacitor may change with temperature and the specific process, creating additional implications such as then requiring a large loop filter capacitor.
Further, it is known that a conventional PLL uses a replica circuit for VCO swing control. Although the use of such a replica circuit is not deficient in the operation of the conventional PLL, the replica circuit serves to provide a control voltage which imposes constant VCO swing amplitude for different oscillation frequencies, temperatures, and process corners. These provisions from this replica circuit for a fixed swing, for example, thereby create the situation that the conventional PLL may lack symmetrical VCO output waveform; this deficiency, which introduces a DC-component and consequently can be up-converted nonlinearly to become high-frequency jitter, is clearly problematic.
Additionally, since a typical conventional PLL employs both a V-I converter and a replica circuit, the total power delivered to V-I converter plus VCO and the replica circuit is dependent on the oscillation frequency. Given such a dependency, it is well-known that consequently, the VCO gain curves for a conventional PLL may exhibit a large variation as between different temperatures and process corners.
Further, in a conventional PLL, the VCO has only one loop-back constraint for each clock phase in the VCO ring oscillator. As a result, the duty cycle distortion in each clock phase becomes unavoidable for high frequency operations, in part since a process mismatch exists between each VCO cell. To overcome this problem, it is common to include a duty cycle corrector circuit in the conventional PLL. However, this additional inclusion can create additional burdens, costs and complexities in the application of the conventional PLL.
The problems described herein are serious and are well-known in the art. It is therefore desirous to provide a PLL that is able to generate 50% duty cycle clocks, regardless of temperature and process variations. It is also desirous to provide a PLL that is able to tolerate external long loop delay time when applying to high-speed memory interfaces. Further, of particular concern and need is overcoming the limitations of the art by determining a phase-locked loop for generation of clocks having a 50% duty cycle for application in high-speed memory interface having an external long loop delay, while avoiding a mandatory requirement for a V-I circuit, effectively keeping the closed-loop phase margin insensitive to loop delay time, not necessitating a replica circuit, and providing a PLL having an improved distribution of VCO gain curves.